diff --git a/src/virgl_hw.h b/src/virgl_hw.h index ee0e0e5..024f7c7 100644 --- a/src/virgl_hw.h +++ b/src/virgl_hw.h @@ -246,6 +246,7 @@ enum virgl_formats { #define VIRGL_CAP_INDIRECT_PARAMS (1 << 22) #define VIRGL_CAP_TRANSFORM_FEEDBACK3 (1 << 23) #define VIRGL_CAP_3D_ASTC (1 << 24) +#define VIRGL_CAP_INDIRECT_INPUT_ADDR (1 << 25) /* virgl bind flags - these are compatible with mesa 10.5 gallium. * but are fixed, no other should be passed to virgl either. diff --git a/src/vrend_renderer.c b/src/vrend_renderer.c index f5d3244..17408fe 100644 --- a/src/vrend_renderer.c +++ b/src/vrend_renderer.c @@ -8734,8 +8734,10 @@ static void vrend_renderer_fill_caps_v2(int gl_ver, int gles_ver, union virgl_c if (has_feature(feat_texture_barrier)) caps->v2.capability_bits |= VIRGL_CAP_TEXTURE_BARRIER; - /* always enable this since it doesn't require an ext to pass tests */ - caps->v2.capability_bits |= VIRGL_CAP_TGSI_COMPONENTS; + /* If we enable input arrays and don't have enhanced layouts then we + * can't support components. */ + if (has_feature(feat_enhanced_layouts)) + caps->v2.capability_bits |= VIRGL_CAP_TGSI_COMPONENTS; if (has_feature(feat_srgb_write_control)) caps->v2.capability_bits |= VIRGL_CAP_SRGB_WRITE_CONTROL; @@ -8794,6 +8796,8 @@ static void vrend_renderer_fill_caps_v2(int gl_ver, int gles_ver, union virgl_c if (epoxy_has_gl_extension("GL_KHR_texture_compression_astc_sliced_3d")) caps->v2.capability_bits |= VIRGL_CAP_3D_ASTC; + + caps->v2.capability_bits |= VIRGL_CAP_INDIRECT_INPUT_ADDR; } void vrend_renderer_fill_caps(uint32_t set, UNUSED uint32_t version, diff --git a/src/vrend_shader.c b/src/vrend_shader.c index ea85c88..ec824b5 100644 --- a/src/vrend_shader.c +++ b/src/vrend_shader.c @@ -4262,7 +4262,6 @@ iter_instruction(struct tgsi_iterate_context *iter, if (require_enhanced_layouts) { ctx->shader_req_bits |= SHADER_REQ_ENHANCED_LAYOUTS; - ctx->shader_req_bits |= SHADER_REQ_SEPERATE_SHADER_OBJECTS; } /* Vertex shader inputs are not send as arrays, but the access may still be