diff --git a/src/gallium/auxiliary/tgsi/tgsi_info.c b/src/gallium/auxiliary/tgsi/tgsi_info.c index b0c385b..47e92ae 100644 --- a/src/gallium/auxiliary/tgsi/tgsi_info.c +++ b/src/gallium/auxiliary/tgsi/tgsi_info.c @@ -264,6 +264,40 @@ static const struct tgsi_opcode_info opcode_info[TGSI_OPCODE_LAST] = { 1, 1, 0, 0, 0, 0, COMP, "DSSG", TGSI_OPCODE_DSSG }, { 1, 2, 0, 0, 0, 0, COMP, "DDIV", TGSI_OPCODE_DDIV }, { 1, 0, 0, 0, 0, 0, OTHR, "CLOCK", TGSI_OPCODE_CLOCK } + + { 1, 1, 0, 0, 0, 0, COMP, "I64ABS", TGSI_OPCODE_I64ABS }, + { 1, 1, 0, 0, 0, 0, COMP, "I64NEG", TGSI_OPCODE_I64NEG }, + { 1, 1, 0, 0, 0, 0, COMP, "I64SSG", TGSI_OPCODE_I64SSG }, + { 1, 2, 0, 0, 0, 0, COMP, "I64SLT", TGSI_OPCODE_I64SLT }, + { 1, 2, 0, 0, 0, 0, COMP, "I64SGE", TGSI_OPCODE_I64SGE }, + { 1, 2, 0, 0, 0, 0, COMP, "I64MIN", TGSI_OPCODE_I64MIN }, + { 1, 2, 0, 0, 0, 0, COMP, "I64MAX", TGSI_OPCODE_I64MAX }, + { 1, 2, 0, 0, 0, 0, COMP, "I64SHR", TGSI_OPCODE_I64SHR }, + { 1, 2, 0, 0, 0, 0, COMP, "I64DIV", TGSI_OPCODE_I64DIV }, + { 1, 2, 0, 0, 0, 0, COMP, "I64MOD", TGSI_OPCODE_I64MOD }, + { 1, 1, 0, 0, 0, 0, COMP, "F2I64", TGSI_OPCODE_F2I64 }, + { 1, 1, 0, 0, 0, 0, COMP, "U2I64", TGSI_OPCODE_U2I64 }, + { 1, 1, 0, 0, 0, 0, COMP, "I2I64", TGSI_OPCODE_I2I64 }, + { 1, 1, 0, 0, 0, 0, COMP, "D2I64", TGSI_OPCODE_D2I64 }, + { 1, 1, 0, 0, 0, 0, COMP, "I642F", TGSI_OPCODE_I642F }, + { 1, 1, 0, 0, 0, 0, COMP, "I642D", TGSI_OPCODE_I642D }, + + { 1, 2, 0, 0, 0, 0, COMP, "U64ADD", TGSI_OPCODE_U64ADD }, + { 1, 2, 0, 0, 0, 0, COMP, "U64MUL", TGSI_OPCODE_U64MUL }, + { 1, 2, 0, 0, 0, 0, COMP, "U64SEQ", TGSI_OPCODE_U64SEQ }, + { 1, 2, 0, 0, 0, 0, COMP, "U64SNE", TGSI_OPCODE_U64SNE }, + { 1, 2, 0, 0, 0, 0, COMP, "U64SLT", TGSI_OPCODE_U64SLT }, + { 1, 2, 0, 0, 0, 0, COMP, "U64SGE", TGSI_OPCODE_U64SGE }, + { 1, 2, 0, 0, 0, 0, COMP, "U64MIN", TGSI_OPCODE_U64MIN }, + { 1, 2, 0, 0, 0, 0, COMP, "U64MAX", TGSI_OPCODE_U64MAX }, + { 1, 2, 0, 0, 0, 0, COMP, "U64SHL", TGSI_OPCODE_U64SHL }, + { 1, 2, 0, 0, 0, 0, COMP, "U64SHR", TGSI_OPCODE_U64SHR }, + { 1, 2, 0, 0, 0, 0, COMP, "U64DIV", TGSI_OPCODE_U64DIV }, + { 1, 2, 0, 0, 0, 0, COMP, "U64MOD", TGSI_OPCODE_U64MOD }, + { 1, 1, 0, 0, 0, 0, COMP, "F2U64", TGSI_OPCODE_F2U64 }, + { 1, 1, 0, 0, 0, 0, COMP, "D2U64", TGSI_OPCODE_D2U64 }, + { 1, 1, 0, 0, 0, 0, COMP, "U642F", TGSI_OPCODE_U642F }, + { 1, 1, 0, 0, 0, 0, COMP, "U642D", TGSI_OPCODE_U642D }, }; const struct tgsi_opcode_info * @@ -277,7 +311,7 @@ tgsi_get_opcode_info( uint opcode ) for (i = 0; i < Elements(opcode_info); i++) assert(opcode_info[i].opcode == i); } - + if (opcode < TGSI_OPCODE_LAST) return &opcode_info[opcode]; @@ -384,6 +418,12 @@ tgsi_opcode_infer_type( uint opcode ) case TGSI_OPCODE_LSB: case TGSI_OPCODE_POPC: case TGSI_OPCODE_UMSB: + case TGSI_OPCODE_U64SEQ: + case TGSI_OPCODE_U64SNE: + case TGSI_OPCODE_U64SLT: + case TGSI_OPCODE_U64SGE: + case TGSI_OPCODE_I64SLT: + case TGSI_OPCODE_I64SGE: return TGSI_TYPE_SIGNED; case TGSI_OPCODE_DADD: case TGSI_OPCODE_DABS: @@ -408,7 +448,33 @@ tgsi_opcode_infer_type( uint opcode ) case TGSI_OPCODE_F2D: case TGSI_OPCODE_I2D: case TGSI_OPCODE_U2D: + case TGSI_OPCODE_U642D: + case TGSI_OPCODE_I642D: return TGSI_TYPE_DOUBLE; + case TGSI_OPCODE_U64MAX: + case TGSI_OPCODE_U64MIN: + case TGSI_OPCODE_U64ADD: + case TGSI_OPCODE_U64MUL: + case TGSI_OPCODE_U64DIV: + case TGSI_OPCODE_U64MOD: + case TGSI_OPCODE_U64SHL: + case TGSI_OPCODE_U64SHR: + case TGSI_OPCODE_F2U64: + case TGSI_OPCODE_D2U64: + return TGSI_TYPE_UNSIGNED64; + case TGSI_OPCODE_I64MAX: + case TGSI_OPCODE_I64MIN: + case TGSI_OPCODE_I64ABS: + case TGSI_OPCODE_I64SSG: + case TGSI_OPCODE_I64NEG: + case TGSI_OPCODE_I64SHR: + case TGSI_OPCODE_I64DIV: + case TGSI_OPCODE_I64MOD: + case TGSI_OPCODE_F2I64: + case TGSI_OPCODE_U2I64: + case TGSI_OPCODE_I2I64: + case TGSI_OPCODE_D2I64: + return TGSI_TYPE_SIGNED64; default: return TGSI_TYPE_FLOAT; } @@ -433,10 +499,12 @@ tgsi_opcode_infer_src_type( uint opcode ) case TGSI_OPCODE_SAMPLE_I_MS: case TGSI_OPCODE_UMUL_HI: case TGSI_OPCODE_UMSB: + case TGSI_OPCODE_U2I64: return TGSI_TYPE_UNSIGNED; case TGSI_OPCODE_IMUL_HI: case TGSI_OPCODE_I2F: case TGSI_OPCODE_I2D: + case TGSI_OPCODE_I2I64: return TGSI_TYPE_SIGNED; case TGSI_OPCODE_ARL: case TGSI_OPCODE_ARR: @@ -449,6 +517,8 @@ tgsi_opcode_infer_src_type( uint opcode ) case TGSI_OPCODE_FSLT: case TGSI_OPCODE_FSNE: case TGSI_OPCODE_UCMP: + case TGSI_OPCODE_F2U64: + case TGSI_OPCODE_F2I64: return TGSI_TYPE_FLOAT; case TGSI_OPCODE_D2F: case TGSI_OPCODE_D2U: @@ -457,7 +527,21 @@ tgsi_opcode_infer_src_type( uint opcode ) case TGSI_OPCODE_DSGE: case TGSI_OPCODE_DSLT: case TGSI_OPCODE_DSNE: + case TGSI_OPCODE_D2U64: + case TGSI_OPCODE_D2I64: return TGSI_TYPE_DOUBLE; + case TGSI_OPCODE_U64SEQ: + case TGSI_OPCODE_U64SNE: + case TGSI_OPCODE_U64SLT: + case TGSI_OPCODE_U64SGE: + case TGSI_OPCODE_U642F: + case TGSI_OPCODE_U642D: + return TGSI_TYPE_UNSIGNED64; + case TGSI_OPCODE_I64SLT: + case TGSI_OPCODE_I64SGE: + case TGSI_OPCODE_I642F: + case TGSI_OPCODE_I642D: + return TGSI_TYPE_SIGNED64; default: return tgsi_opcode_infer_type(opcode); } diff --git a/src/gallium/auxiliary/tgsi/tgsi_info.h b/src/gallium/auxiliary/tgsi/tgsi_info.h index aa7edd1..5e4fa84 100644 --- a/src/gallium/auxiliary/tgsi/tgsi_info.h +++ b/src/gallium/auxiliary/tgsi/tgsi_info.h @@ -97,7 +97,9 @@ enum tgsi_opcode_type { TGSI_TYPE_UNSIGNED, TGSI_TYPE_SIGNED, TGSI_TYPE_FLOAT, - TGSI_TYPE_DOUBLE + TGSI_TYPE_DOUBLE, + TGSI_TYPE_UNSIGNED64, + TGSI_TYPE_SIGNED64 }; enum tgsi_opcode_type diff --git a/src/gallium/include/pipe/p_shader_tokens.h b/src/gallium/include/pipe/p_shader_tokens.h index acfbeb5..bedad2a 100644 --- a/src/gallium/include/pipe/p_shader_tokens.h +++ b/src/gallium/include/pipe/p_shader_tokens.h @@ -571,7 +571,43 @@ struct tgsi_property_data { #define TGSI_OPCODE_DSSG 222 #define TGSI_OPCODE_DDIV 223 #define TGSI_OPCODE_CLOCK 224 -#define TGSI_OPCODE_LAST 225 + +/* opcodes for ARB_gpu_shader_int64 */ +#define TGSI_OPCODE_I64ABS 225 +#define TGSI_OPCODE_I64NEG 226 +#define TGSI_OPCODE_I64SSG 227 +#define TGSI_OPCODE_I64SLT 228 +#define TGSI_OPCODE_I64SGE 229 +#define TGSI_OPCODE_I64MIN 230 +#define TGSI_OPCODE_I64MAX 231 +#define TGSI_OPCODE_I64SHR 232 +#define TGSI_OPCODE_I64DIV 233 +#define TGSI_OPCODE_I64MOD 234 +#define TGSI_OPCODE_F2I64 235 +#define TGSI_OPCODE_U2I64 236 +#define TGSI_OPCODE_I2I64 237 +#define TGSI_OPCODE_D2I64 238 +#define TGSI_OPCODE_I642F 239 +#define TGSI_OPCODE_I642D 240 + +#define TGSI_OPCODE_U64ADD 241 +#define TGSI_OPCODE_U64MUL 242 +#define TGSI_OPCODE_U64SEQ 243 +#define TGSI_OPCODE_U64SNE 244 +#define TGSI_OPCODE_U64SLT 245 +#define TGSI_OPCODE_U64SGE 246 +#define TGSI_OPCODE_U64MIN 247 +#define TGSI_OPCODE_U64MAX 248 +#define TGSI_OPCODE_U64SHL 249 +#define TGSI_OPCODE_U64SHR 250 +#define TGSI_OPCODE_U64DIV 251 +#define TGSI_OPCODE_U64MOD 252 +#define TGSI_OPCODE_F2U64 253 +#define TGSI_OPCODE_D2U64 254 +#define TGSI_OPCODE_U642F 255 +#define TGSI_OPCODE_U642D 256 + +#define TGSI_OPCODE_LAST 257 /** * Opcode is the operation code to execute. A given operation defines the